Type Members

1.  class Cache_op extends Lsu_isa

   the operation that dcache support

   the operation that dcache support

   Note

   Lsu isa

   ,

   probe

   ,

   grant

   ,

   preft

2.  class Dcache extends DcacheBase with DcacheScoreBoard
3.  abstract class DcacheBase extends DcacheModule
4.  trait DcacheScoreBoard extends AnyRef
5.  class DcacheStage extends DcacheStageBase with DcacheStageSRAM with DcacheStageLRSC with DcacheStageWData with DcacheStageBlock with DcacheStageRTN
6.  class DcacheStageBase extends DcacheModule
7.  trait DcacheStageBlock extends AnyRef
8.  trait DcacheStageLRSC extends AnyRef
9.  trait DcacheStageRTN extends AnyRef
10.  trait DcacheStageSRAM extends AnyRef
11.  trait DcacheStageWData extends AnyRef
12.  class Dcache_Deq_Bundle extends Dcache_ScoreBoard_Bundle
13.  class Dcache_Enq_Bundle extends Dcache_ScoreBoard_Bundle
14.  abstract class Dcache_ScoreBoard_Bundle extends DcacheBundle
15.  class FakeProbeUnit extends RiftModule
16.  class GetUnit extends RiftModule with HasDcacheParameters

    The Queue of cache to request acquire and waiting for grant and ack grant Get-Mode

17.  class IO_Lsu extends RiftModule
18.  class Info_miss_req extends RiftBundle
19.  class Info_miss_rsp extends RiftBundle with HasDcacheParameters
20.  class Info_probe_req extends RiftBundle
21.  class Info_writeBack_req extends RiftBundle with HasDcacheParameters

    the operation infomation of writeback Unit

22.  trait LSU_AddrTrans extends AnyRef

    request mmu and get the paddr

23.  trait LSU_CacheMux extends AnyRef

    depending on the paddr, the cache request will be divided into 4 or 8 (nm) "bank"

24.  trait LSU_Fault extends AnyRef
25.  trait LSU_LsArb extends AnyRef

    Merge the request from 1) opMux (load is bypassing the stQueue) 2) store and amo form stQueue

26.  trait LSU_Mem extends AnyRef
27.  trait LSU_OpMux extends AnyRef

    Mux store load amo request into three different ways

28.  trait LSU_RegionMux extends AnyRef

    Mux request to three different region, cache, system, periph depending on paddr

29.  trait LSU_StQueue extends AnyRef

    for store and amo, they should be push into stQueue waiting for commited and pending commit

30.  trait LSU_WriteBack extends AnyRef
31.  class Lsu extends LsuBase with LSU_AddrTrans with LSU_OpMux with LSU_StQueue with LSU_LsArb with LSU_RegionMux with LSU_CacheMux with LSU_Mem with LSU_WriteBack with LSU_Fault
32.  abstract class LsuBase extends DcacheModule with HasFPUParameters
33.  class MissUnit extends RiftModule with HasDcacheParameters

    The Queue of cache to request acquire and waiting for grant and ack grant

34.  class ProbeUnit extends RiftModule

    ProbeUnit will accept probe request from l2cache and forward it to l1cache to resp data

35.  class ProbeUnitIO extends RiftBundle
36.  class PutUnit extends RiftModule with HasDcacheParameters

    a writeBack Unit accept data and paddr from l1cache and write it back to l2cache Put-Mode

37.  class Store_queue extends Stq_Base with Stq_Ptr with Stq_Overlap

    bound to every cache

38.  abstract class Stq_Base extends DcacheModule
39.  trait Stq_Overlap extends AnyRef
40.  trait Stq_Ptr extends AnyRef
41.  class WriteBackUnit extends RiftModule with HasDcacheParameters

    a writeBack Unit accept data and paddr from l1cache and write it back to l2cache Probe-Release-Mode