class Store_queue extends Stq_Base with Stq_Ptr with Stq_Overlap
bound to every cache
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- new Store_queue()(implicit p: Parameters)
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- def bk: Int
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- def cmChn: Int
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- val cm_ptr: UInt
- Definition Classes
- Stq_Base
- val cm_ptr_reg: UInt
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- val dcacheParams: DcacheParameters
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- def l1BeatBits: Int
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- def opChn: Int
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- val overlap_buff: Vec[Lsu_iss_info]
- Definition Classes
- Stq_Overlap
- implicit val p: Parameters
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- def parentModName: String
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- def parentPathName: String
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- def plen: Int
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- def pmpNum: Int
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- def portsContains(elem: Data): Boolean
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- def portsSize: Int
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- val rd_buff: Lsu_iss_info
- Definition Classes
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- val rd_ptr: UInt
- Definition Classes
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- val rd_ptr_reg: UInt
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- Stq_Base
- final val reset: Reset
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- def resetType: Type
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- val riftSetting: RiftSetting
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- def rnChn: Int
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- def sbEntry: Int
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- def stEntry: Int
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- def st_w: Int
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- Stq_Base
- def suggestName(seed: => String): Store_queue.this.type
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- final def synchronized[T0](arg0: => T0): T0
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- val temp_wdata: Vec[UInt]
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- def tlbEntry: Int
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- val vParams: VectorParameters
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- def vRegNum: Int
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- def wbChn: Int
- Definition Classes
- HasRiftParameters
- val wr_ptr: UInt
- Definition Classes
- Stq_Base
- val wr_ptr_reg: UInt
- Definition Classes
- Stq_Base
- def xRegNum: Int
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Deprecated Value Members
- def finalize(): Unit
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- def override_clock: Option[Clock]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation