class Store_queue extends Stq_Base with Stq_Ptr with Stq_Overlap

bound to every cache

Linear Supertypes
Stq_Overlap, Stq_Ptr, Stq_Base, DcacheModule, HasDcacheParameters, HasRiftParameters, Module, RawModule, BaseModule, IsInstantiable, HasId, InstanceId, AnyRef, Any
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Inherited
  1. Store_queue
  2. Stq_Overlap
  3. Stq_Ptr
  4. Stq_Base
  5. DcacheModule
  6. HasDcacheParameters
  7. HasRiftParameters
  8. Module
  9. RawModule
  10. BaseModule
  11. IsInstantiable
  12. HasId
  13. InstanceId
  14. AnyRef
  15. Any
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new Store_queue()(implicit p: Parameters)

Type Members

  1. class StqIO extends Bundle
    Definition Classes
    Stq_Base

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _moduleDefinitionIdentifierProposal: String
    Attributes
    protected
    Definition Classes
    BaseModule
  8. def _traitModuleDefinitionIdentifierProposal: Option[String]
    Attributes
    protected
    Definition Classes
    BaseModule
  9. def addr_lsb: Int
    Definition Classes
    HasDcacheParameters
  10. def aluNum: Int
    Definition Classes
    HasRiftParameters
  11. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  12. def bk: Int
    Definition Classes
    HasDcacheParameters
  13. def bk_w: Int
    Definition Classes
    HasDcacheParameters
  14. val buff: Vec[Lsu_iss_info]
    Definition Classes
    Stq_Base
  15. def cb: Int
    Definition Classes
    HasDcacheParameters
  16. def cb_w: Int
    Definition Classes
    HasDcacheParameters
  17. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  18. def cl: Int
    Definition Classes
    HasDcacheParameters
  19. final val clock: Clock
    Definition Classes
    Module
  20. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
  21. def cmChn: Int
    Definition Classes
    HasRiftParameters
  22. val cm_ptr: UInt
    Definition Classes
    Stq_Base
  23. val cm_ptr_reg: UInt
    Definition Classes
    Stq_Base
  24. val dcacheParams: DcacheParameters
    Definition Classes
    HasRiftParameters
  25. final val definitionIdentifier: String
    Definition Classes
    BaseModule
  26. def desiredName: String
    Definition Classes
    BaseModule
  27. def dptEntry: Int
    Definition Classes
    HasRiftParameters
  28. def dw: Int
    Definition Classes
    HasDcacheParameters
  29. val emty: Bool
    Definition Classes
    Stq_Base
  30. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  31. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  32. def fRegNum: Int
    Definition Classes
    HasRiftParameters
  33. def fpuNum: Int
    Definition Classes
    HasRiftParameters
  34. def ftChn: Int
    Definition Classes
    HasRiftParameters
  35. val full: Bool
    Definition Classes
    Stq_Base
  36. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  37. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  38. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  39. def hasDebugger: Boolean
    Definition Classes
    HasRiftParameters
  40. def hasL2: Boolean
    Definition Classes
    HasRiftParameters
  41. def hasLRU: Boolean
    Definition Classes
    HasRiftParameters
  42. def hasPreFetch: Boolean
    Definition Classes
    HasRiftParameters
  43. def hasSeed: Boolean
    Definition Classes
    HasId
  44. def hasVector: Boolean
    Definition Classes
    HasRiftParameters
  45. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  46. def hasuBTB: Boolean
    Definition Classes
    HasRiftParameters
  47. def hpmNum: Int
    Definition Classes
    HasRiftParameters
  48. val icacheParams: IcacheParameters
    Definition Classes
    HasRiftParameters
  49. val ifParams: IFParameters
    Definition Classes
    HasRiftParameters
  50. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  51. val io: StqIO
    Definition Classes
    Stq_BaseDcacheModule
  52. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  53. def isLowPower: Boolean
    Definition Classes
    HasRiftParameters
  54. def isMinArea: Boolean
    Definition Classes
    HasRiftParameters
  55. val is_amo: Bool
    Definition Classes
    Stq_Base
  56. val is_st_commited: Vec[Bool]
    Definition Classes
    Stq_Ptr
  57. def l1BeatBits: Int
    Definition Classes
    HasRiftParameters
  58. def l1DW: Int
    Definition Classes
    HasRiftParameters
  59. def line_w: Int
    Definition Classes
    HasDcacheParameters
  60. def maxRegNum: Int
    Definition Classes
    HasRiftParameters
  61. def memBeatBits: Int
    Definition Classes
    HasRiftParameters
  62. def mulNum: Int
    Definition Classes
    HasRiftParameters
  63. final lazy val name: String
    Definition Classes
    BaseModule
  64. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  65. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  66. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  67. def opChn: Int
    Definition Classes
    HasRiftParameters
  68. val overlap_buff: Vec[Lsu_iss_info]
    Definition Classes
    Stq_Overlap
  69. implicit val p: Parameters
    Definition Classes
    DcacheModuleHasRiftParameters
  70. def parentModName: String
    Definition Classes
    HasId → InstanceId
  71. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  72. def pathName: String
    Definition Classes
    HasId → InstanceId
  73. def plen: Int
    Definition Classes
    HasRiftParameters
  74. def pmpNum: Int
    Definition Classes
    HasRiftParameters
  75. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  76. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  77. val rd_buff: Lsu_iss_info
    Definition Classes
    Stq_Base
  78. val rd_ptr: UInt
    Definition Classes
    Stq_Base
  79. val rd_ptr_reg: UInt
    Definition Classes
    Stq_Base
  80. final val reset: Reset
    Definition Classes
    Module
  81. def resetType: Type
    Definition Classes
    Module
  82. val riftSetting: RiftSetting
    Definition Classes
    HasRiftParameters
  83. def rnChn: Int
    Definition Classes
    HasRiftParameters
  84. def sbEntry: Int
    Definition Classes
    HasDcacheParameters
  85. def stEntry: Int
    Definition Classes
    HasDcacheParameters
  86. def st_w: Int
    Definition Classes
    Stq_Base
  87. def suggestName(seed: => String): Store_queue.this.type
    Definition Classes
    HasId
  88. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  89. def tag_w: Int
    Definition Classes
    HasDcacheParameters
  90. val temp_wdata: Vec[UInt]
    Definition Classes
    Stq_Overlap
  91. val temp_wstrb: Vec[UInt]
    Definition Classes
    Stq_Overlap
  92. def tlbEntry: Int
    Definition Classes
    HasRiftParameters
  93. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  94. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  95. def toString(): String
    Definition Classes
    AnyRef → Any
  96. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  97. val vParams: VectorParameters
    Definition Classes
    HasRiftParameters
  98. def vRegNum: Int
    Definition Classes
    HasRiftParameters
  99. def vlen: Int
    Definition Classes
    HasRiftParameters
  100. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  101. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException]) @native()
  102. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  103. def wbChn: Int
    Definition Classes
    HasRiftParameters
  104. val wr_ptr: UInt
    Definition Classes
    Stq_Base
  105. val wr_ptr_reg: UInt
    Definition Classes
    Stq_Base
  106. def xRegNum: Int
    Definition Classes
    HasRiftParameters

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable]) @Deprecated
    Deprecated
  2. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  3. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

Inherited from Stq_Overlap

Inherited from Stq_Ptr

Inherited from Stq_Base

Inherited from DcacheModule

Inherited from HasDcacheParameters

Inherited from HasRiftParameters

Inherited from Module

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped