class MissUnit extends RiftModule with HasDcacheParameters

The Queue of cache to request acquire and waiting for grant and ack grant

Linear Supertypes
HasDcacheParameters, RiftModule, HasRiftParameters, Module, RawModule, BaseModule, IsInstantiable, HasId, InstanceId, AnyRef, Any
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  2. By Inheritance
Inherited
  1. MissUnit
  2. HasDcacheParameters
  3. RiftModule
  4. HasRiftParameters
  5. Module
  6. RawModule
  7. BaseModule
  8. IsInstantiable
  9. HasId
  10. InstanceId
  11. AnyRef
  12. Any
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new MissUnit(edge: TLEdgeOut, setting: Int, id: Int)(implicit p: Parameters)

Type Members

  1. class MissUnitIO extends Bundle

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _moduleDefinitionIdentifierProposal: String
    Attributes
    protected
    Definition Classes
    BaseModule
  8. def _traitModuleDefinitionIdentifierProposal: Option[String]
    Attributes
    protected
    Definition Classes
    BaseModule
  9. val acquire_sel: UInt

    when the bus is free, a valid paddr will be selected to emit

  10. def addr_lsb: Int
    Definition Classes
    HasDcacheParameters
  11. def aluNum: Int
    Definition Classes
    HasRiftParameters
  12. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  13. def bk: Int
    Definition Classes
    HasDcacheParameters
  14. def bk_w: Int
    Definition Classes
    HasDcacheParameters
  15. val cache_acquire_vaild: Bool

    a register of io.cache_acquire.valid

  16. val cache_grantAck_valid: Bool

    a register of io.cache_grantAck.valid

  17. val cache_grant_ready: Bool

    a wire of io.cache_grant.ready

  18. val cache_grant_reg: TLBundleD
  19. def cb: Int
    Definition Classes
    HasDcacheParameters
  20. def cb_w: Int
    Definition Classes
    HasDcacheParameters
  21. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  22. def cl: Int
    Definition Classes
    HasDcacheParameters
  23. final val clock: Clock
    Definition Classes
    Module
  24. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
  25. def cmChn: Int
    Definition Classes
    HasRiftParameters
  26. val dcacheParams: DcacheParameters
    Definition Classes
    HasRiftParameters
  27. final val definitionIdentifier: String
    Definition Classes
    BaseModule
  28. def desiredName: String
    Definition Classes
    BaseModule
  29. def dptEntry: Int
    Definition Classes
    HasRiftParameters
  30. def dw: Int
    Definition Classes
    HasDcacheParameters
  31. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  32. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  33. def fRegNum: Int
    Definition Classes
    HasRiftParameters
  34. def fpuNum: Int
    Definition Classes
    HasRiftParameters
  35. def ftChn: Int
    Definition Classes
    HasRiftParameters
  36. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  37. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  38. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  39. def hasDebugger: Boolean
    Definition Classes
    HasRiftParameters
  40. def hasL2: Boolean
    Definition Classes
    HasRiftParameters
  41. def hasLRU: Boolean
    Definition Classes
    HasRiftParameters
  42. def hasPreFetch: Boolean
    Definition Classes
    HasRiftParameters
  43. def hasSeed: Boolean
    Definition Classes
    HasId
  44. def hasVector: Boolean
    Definition Classes
    HasRiftParameters
  45. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  46. def hasuBTB: Boolean
    Definition Classes
    HasRiftParameters
  47. def hpmNum: Int
    Definition Classes
    HasRiftParameters
  48. val icacheParams: IcacheParameters
    Definition Classes
    HasRiftParameters
  49. val ifParams: IFParameters
    Definition Classes
    HasRiftParameters
  50. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  51. val io: MissUnitIO
    Definition Classes
    MissUnitRiftModule
  52. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  53. def isLowPower: Boolean
    Definition Classes
    HasRiftParameters
  54. def isMinArea: Boolean
    Definition Classes
    HasRiftParameters
  55. val is_merge: Bool

    findout if there is no buff is valid and has the same paddr, or merge it!

  56. val is_missQueue_full: Bool

    when all missQueue BUFF is in used, miss req will be bypassed

  57. val is_trans_done: Bool

  58. def l1BeatBits: Int
    Definition Classes
    HasRiftParameters
  59. def l1DW: Int
    Definition Classes
    HasRiftParameters
  60. def line_w: Int
    Definition Classes
    HasDcacheParameters
  61. val load_sel: UInt

    select an empty buff to load paddr, except when *buff full* or *can merge*

  62. def maxRegNum: Int
    Definition Classes
    HasRiftParameters
  63. def memBeatBits: Int
    Definition Classes
    HasRiftParameters
  64. val miss_queue: Vec[Info_miss_req]

    a parallel buff of *paddr* miss request, when a duplicated request comes, it will be acked but dismiss

  65. val miss_rsp: Vec[UInt]

    a grant will complete in 2 beat, and get 256-bits data

  66. val miss_valid: Vec[Bool]

    a valid flag indicated whether a buff is in-used

  67. val mshr_state_dnxt: UInt
  68. val mshr_state_qout: UInt
  69. def mulNum: Int
    Definition Classes
    HasRiftParameters
  70. final lazy val name: String
    Definition Classes
    BaseModule
  71. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  72. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  73. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  74. def opChn: Int
    Definition Classes
    HasRiftParameters
  75. implicit val p: Parameters
    Definition Classes
    RiftModuleHasRiftParameters
  76. def parentModName: String
    Definition Classes
    HasId → InstanceId
  77. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  78. def pathName: String
    Definition Classes
    HasId → InstanceId
  79. def plen: Int
    Definition Classes
    HasRiftParameters
  80. def pmpNum: Int
    Definition Classes
    HasRiftParameters
  81. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  82. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  83. final val reset: Reset
    Definition Classes
    Module
  84. def resetType: Type
    Definition Classes
    Module
  85. val riftSetting: RiftSetting
    Definition Classes
    HasRiftParameters
  86. def rnChn: Int
    Definition Classes
    HasRiftParameters
  87. val rsp_valid: Bool

    a register of io.rsp.valid

  88. def sbEntry: Int
    Definition Classes
    HasDcacheParameters
  89. def stEntry: Int
    Definition Classes
    HasDcacheParameters
  90. def suggestName(seed: => String): MissUnit.this.type
    Definition Classes
    HasId
  91. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  92. def tag_w: Int
    Definition Classes
    HasDcacheParameters
  93. def tlbEntry: Int
    Definition Classes
    HasRiftParameters
  94. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  95. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  96. def toString(): String
    Definition Classes
    AnyRef → Any
  97. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  98. val transCnt: UInt

  99. val vParams: VectorParameters
    Definition Classes
    HasRiftParameters
  100. def vRegNum: Int
    Definition Classes
    HasRiftParameters
  101. def vlen: Int
    Definition Classes
    HasRiftParameters
  102. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  103. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException]) @native()
  104. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  105. def wbChn: Int
    Definition Classes
    HasRiftParameters
  106. def xRegNum: Int
    Definition Classes
    HasRiftParameters

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable]) @Deprecated
    Deprecated
  2. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  3. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

Inherited from HasDcacheParameters

Inherited from RiftModule

Inherited from HasRiftParameters

Inherited from Module

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped