class Lsu extends LsuBase with LSU_AddrTrans with LSU_OpMux with LSU_StQueue with LSU_LsArb with LSU_RegionMux with LSU_CacheMux with LSU_Mem with LSU_WriteBack with LSU_Fault
Linear Supertypes
Ordering
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Inherited
- Lsu
- LSU_Fault
- LSU_WriteBack
- LSU_Mem
- LSU_CacheMux
- LSU_RegionMux
- LSU_LsArb
- LSU_StQueue
- LSU_OpMux
- LSU_AddrTrans
- LsuBase
- HasFPUParameters
- DcacheModule
- HasDcacheParameters
- HasRiftParameters
- Module
- RawModule
- BaseModule
- IsInstantiable
- HasId
- InstanceId
- AnyRef
- Any
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Visibility
- Public
- Protected
Instance Constructors
- new Lsu(edge: Seq[TLEdgeOut])(implicit p: Parameters)
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- val CacheMuxBits: Dcache_Enq_Bundle
- Definition Classes
- LSU_CacheMux
- def D: UInt
- Definition Classes
- HasFPUParameters
- def I: UInt
- Definition Classes
- HasFPUParameters
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
- Attributes
- protected
- Definition Classes
- BaseModule
- def S: UInt
- Definition Classes
- HasFPUParameters
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _moduleDefinitionIdentifierProposal: String
- Attributes
- protected
- Definition Classes
- BaseModule
- def _traitModuleDefinitionIdentifierProposal: Option[String]
- Attributes
- protected
- Definition Classes
- BaseModule
- val addrTransIO: DecoupledIO[Lsu_iss_info]
decoupled output of addrTrans
decoupled output of addrTrans
- Definition Classes
- LsuBase
- def addr_lsb: Int
- Definition Classes
- HasDcacheParameters
- def aluNum: Int
- Definition Classes
- HasRiftParameters
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def bk: Int
- Definition Classes
- HasDcacheParameters
- def bk_w: Int
- Definition Classes
- HasDcacheParameters
- def box(x: UInt, tag: UInt): UInt
- Definition Classes
- HasFPUParameters
- def box(x: UInt, t: FType): UInt
- Definition Classes
- HasFPUParameters
- val cache: IndexedSeq[Dcache]
- Definition Classes
- LsuBase
- val cacheBankIO: Vec[DecoupledIO[Dcache_Enq_Bundle]]
- Definition Classes
- LsuBase
- def cb: Int
- Definition Classes
- HasDcacheParameters
- def cb_w: Int
- Definition Classes
- HasDcacheParameters
- val chn: UInt
- Definition Classes
- LSU_CacheMux
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- def cl: Int
- Definition Classes
- HasDcacheParameters
- final val clock: Clock
- Definition Classes
- Module
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- def cmChn: Int
- Definition Classes
- HasRiftParameters
- def consistent(x: UInt): Bool
- Definition Classes
- HasFPUParameters
- val dEdge: Seq[TLEdgeOut]
- Definition Classes
- LsuBase
- val dcacheParams: DcacheParameters
- Definition Classes
- HasRiftParameters
- final val definitionIdentifier: String
- Definition Classes
- BaseModule
- def desiredName: String
- Definition Classes
- BaseModule
- def dptEntry: Int
- Definition Classes
- HasRiftParameters
- def dw: Int
- Definition Classes
- HasDcacheParameters
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- val excReg: Info_lsu_cmm
- Definition Classes
- LSU_Fault
- val fLen: Int
- Definition Classes
- HasFPUParameters
- def fRegNum: Int
- Definition Classes
- HasRiftParameters
- val fe_wb_fifo: Queue[WriteBack_info]
- Definition Classes
- LsuBase
- val floatTypes: List[FType]
- Definition Classes
- HasFPUParameters
- val flu_wb_fifo: Queue[WriteBack_info]
- Definition Classes
- LsuBase
- def fpuNum: Int
- Definition Classes
- HasRiftParameters
- val frtn_arb: Arbiter[WriteBack_info]
- Definition Classes
- LsuBase
- def ftChn: Int
- Definition Classes
- HasRiftParameters
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def hasDebugger: Boolean
- Definition Classes
- HasRiftParameters
- def hasL2: Boolean
- Definition Classes
- HasRiftParameters
- def hasLRU: Boolean
- Definition Classes
- HasRiftParameters
- def hasPreFetch: Boolean
- Definition Classes
- HasRiftParameters
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hasVector: Boolean
- Definition Classes
- HasRiftParameters
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def hasuBTB: Boolean
- Definition Classes
- HasRiftParameters
- def hpmNum: Int
- Definition Classes
- HasRiftParameters
- val icacheParams: IcacheParameters
- Definition Classes
- HasRiftParameters
- def ieee(x: UInt, t: FType = FType.D): UInt
- Definition Classes
- HasFPUParameters
- val ifParams: IFParameters
- Definition Classes
- HasRiftParameters
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- val io: LsuIO
- Definition Classes
- LsuBase → DcacheModule
- val irtn_arb: Arbiter[WriteBack_info]
merge lu-writeback and su-writeback
- val isFaultBlock: Bool
- Definition Classes
- LSU_Fault
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- def isLowPower: Boolean
- Definition Classes
- HasRiftParameters
- def isMinArea: Boolean
- Definition Classes
- HasRiftParameters
- val is_empty: Bool
indicate the mem unit is empty by all seq-element is empty
indicate the mem unit is empty by all seq-element is empty
- Definition Classes
- LsuBase
- def l1BeatBits: Int
- Definition Classes
- HasRiftParameters
- def l1DW: Int
- Definition Classes
- HasRiftParameters
- def line_w: Int
- Definition Classes
- HasDcacheParameters
- val ls_arb: Arbiter[Lsu_iss_info]
Merge the request from 1) opMux (load is bypassing the stQueue) 2) store and amo form stQueue
Merge the request from 1) opMux (load is bypassing the stQueue) 2) store and amo form stQueue
- Definition Classes
- LsuBase
- val lu_wb_arb: Arbiter[Dcache_Deq_Bundle]
the load-and-amo operation write-back info from cache or bus
the load-and-amo operation write-back info from cache or bus
- returns
Dcache_Deq_Bundle
- Definition Classes
- LsuBase
- val lu_wb_fifo: Queue[WriteBack_info]
the load-and-amo write-back fifo, flow !!!!!
the load-and-amo write-back fifo, flow !!!!!
- returns
WriteBack_info
- Definition Classes
- LsuBase
- Note
when trans_kill, the load result will be abort here to prevent write-back
- def maxExpWidth: Int
- Definition Classes
- HasFPUParameters
- def maxRegNum: Int
- Definition Classes
- HasRiftParameters
- def maxSigWidth: Int
- Definition Classes
- HasFPUParameters
- def maxType: FType
- Definition Classes
- HasFPUParameters
- def memBeatBits: Int
- Definition Classes
- HasRiftParameters
- val minFLen: Int
- Definition Classes
- HasFPUParameters
- def minType: FType
- Definition Classes
- HasFPUParameters
- val minXLen: Int
- Definition Classes
- HasFPUParameters
- def mulNum: Int
- Definition Classes
- HasRiftParameters
- val nIntTypes: Int
- Definition Classes
- HasFPUParameters
- final lazy val name: String
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- val opAmIO: DecoupledIO[Lsu_iss_info]
- Definition Classes
- LsuBase
- def opChn: Int
- Definition Classes
- HasRiftParameters
- val opLdIO: DecoupledIO[Lsu_iss_info]
- Definition Classes
- LsuBase
- val opStIO: DecoupledIO[Lsu_iss_info]
decoupled output of OP_mux
decoupled output of OP_mux
- Definition Classes
- LsuBase
- implicit val p: Parameters
- Definition Classes
- DcacheModule → HasRiftParameters
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- val periph: IO_Lsu
- Definition Classes
- LsuBase
- def pkg_Dcache_Enq_Bundle(ori: Lsu_iss_info, overlapReq: Stq_req_Bundle, overlapResp: Stq_resp_Bundle)(implicit p: Parameters): Dcache_Enq_Bundle
package write and amo operation
package write and amo operation
- Definition Classes
- LsuBase
- def plen: Int
- Definition Classes
- HasRiftParameters
- def pmpNum: Int
- Definition Classes
- HasRiftParameters
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- def prevType(t: FType): FType
- Definition Classes
- HasFPUParameters
- val psel: UInt
- Definition Classes
- LSU_RegionMux
- def recode(x: UInt, tag: Int): UInt
- Definition Classes
- HasFPUParameters
- val regionDCacheIO: DecoupledIO[Lsu_iss_info]
- Definition Classes
- LsuBase
- val regionPeriphIO: DecoupledIO[Lsu_iss_info]
- Definition Classes
- LsuBase
- val regionSystemIO: DecoupledIO[Lsu_iss_info]
- Definition Classes
- LsuBase
- final val reset: Reset
- Definition Classes
- Module
- def resetType: Type
- Definition Classes
- Module
- val riftSetting: RiftSetting
- Definition Classes
- HasRiftParameters
- def rnChn: Int
- Definition Classes
- HasRiftParameters
- def sanitizeNaN(x: UInt, t: FType): UInt
- Definition Classes
- HasFPUParameters
- def sbEntry: Int
- Definition Classes
- HasDcacheParameters
- val sel: UInt
- Definition Classes
- LSU_RegionMux
- def stEntry: Int
- Definition Classes
- HasDcacheParameters
- val stQueue: Store_queue
for store and amo, they should be push into stQueue waiting for commited and pending commit
for store and amo, they should be push into stQueue waiting for commited and pending commit
- Definition Classes
- LsuBase
- val su_wb_fifo: Queue[WriteBack_info]
store operations will write-back dircetly from opMux, flow !!!!!
store operations will write-back dircetly from opMux, flow !!!!!
- returns
WriteBack_info
- Definition Classes
- LsuBase
- def suggestName(seed: => String): Lsu.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val system: IO_Lsu
- Definition Classes
- LsuBase
- def tag_w: Int
- Definition Classes
- HasDcacheParameters
- def tlbEntry: Int
- Definition Classes
- HasRiftParameters
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- val trans_kill: Bool
when a flush comes, flush all uncommit write & amo request in pending-fifo, and block all request from issue until scoreboard is empty
when a flush comes, flush all uncommit write & amo request in pending-fifo, and block all request from issue until scoreboard is empty
- Definition Classes
- LsuBase
- def typeTag(t: FType): Int
- Definition Classes
- HasFPUParameters
- def typeTagWbOffset: UInt
- Definition Classes
- HasFPUParameters
- def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt
- Definition Classes
- HasFPUParameters
- val vParams: VectorParameters
- Definition Classes
- HasRiftParameters
- def vRegNum: Int
- Definition Classes
- HasRiftParameters
- def vlen: Int
- Definition Classes
- HasRiftParameters
- val vls_wb_fifo: Queue[Vector_WriteBack_Bundle]
- Definition Classes
- LsuBase
- val vrtn_arb: Arbiter[Vector_WriteBack_Bundle]
- Definition Classes
- LsuBase
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- def wbChn: Int
- Definition Classes
- HasRiftParameters
- def xLen: Int
- Definition Classes
- HasFPUParameters
- def xRegNum: Int
- Definition Classes
- HasRiftParameters
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation