class GetUnit extends RiftModule with HasDcacheParameters
The Queue of cache to request acquire and waiting for grant and ack grant Get-Mode
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Instance Constructors
- new GetUnit(edge: TLEdgeOut, id: Int)(implicit p: Parameters)
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
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- final def ##: Int
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- final def ==(arg0: Any): Boolean
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- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
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- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
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- var _closed: Boolean
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- def _moduleDefinitionIdentifierProposal: String
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- BaseModule
- def _traitModuleDefinitionIdentifierProposal: Option[String]
- Attributes
- protected
- Definition Classes
- BaseModule
- val access_ready: Bool
a wire of io.access.ready
- val access_reg: TLBundleD
- val acquire_sel: UInt
when the bus is free, a valid paddr will be selected to emit
- def addr_lsb: Int
- Definition Classes
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- def aluNum: Int
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- final def asInstanceOf[T0]: T0
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- def bk: Int
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- def bk_w: Int
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- def cb: Int
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- def cb_w: Int
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- def circuitName: String
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- def cl: Int
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- final val clock: Clock
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- def clone(): AnyRef
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- protected[lang]
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- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- def cmChn: Int
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- HasRiftParameters
- val dcacheParams: DcacheParameters
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- final val definitionIdentifier: String
- Definition Classes
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- def desiredName: String
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- def dptEntry: Int
- Definition Classes
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- def dw: Int
- Definition Classes
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- final def eq(arg0: AnyRef): Boolean
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- def equals(that: Any): Boolean
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- def fRegNum: Int
- Definition Classes
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- def fpuNum: Int
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- def ftChn: Int
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- final def getClass(): Class[_ <: AnyRef]
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- def getCommands: Seq[Command]
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- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- val getPut_vaild: Bool
a register of io.getPut.valid
- def hasDebugger: Boolean
- Definition Classes
- HasRiftParameters
- def hasL2: Boolean
- Definition Classes
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- def hasLRU: Boolean
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- def hasPreFetch: Boolean
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- def hasSeed: Boolean
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- def hasVector: Boolean
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- def hashCode(): Int
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- def hasuBTB: Boolean
- Definition Classes
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- def hpmNum: Int
- Definition Classes
- HasRiftParameters
- val icacheParams: IcacheParameters
- Definition Classes
- HasRiftParameters
- val ifParams: IFParameters
- Definition Classes
- HasRiftParameters
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- val io: GetUnitIO
- Definition Classes
- GetUnit → RiftModule
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- def isLowPower: Boolean
- Definition Classes
- HasRiftParameters
- def isMinArea: Boolean
- Definition Classes
- HasRiftParameters
- val is_merge: Bool
findout if there is no buff is valid and has the same paddr, or merge it!
- val is_missQueue_full: Bool
when all missQueue BUFF is in used, miss req will be bypassed
- val is_trans_done: Bool
- def l1BeatBits: Int
- Definition Classes
- HasRiftParameters
- def l1DW: Int
- Definition Classes
- HasRiftParameters
- def line_w: Int
- Definition Classes
- HasDcacheParameters
- val load_sel: UInt
select an empty buff to load paddr, except when *buff full* or *can merge*
- def maxRegNum: Int
- Definition Classes
- HasRiftParameters
- def memBeatBits: Int
- Definition Classes
- HasRiftParameters
- val miss_queue: Vec[Info_miss_req]
a parallel buff of *paddr* miss request, when a duplicated request comes, it will be acked but dismiss
- val miss_rsp: Vec[UInt]
a grant will complete in 2 beat, and get 256-bits data
- val miss_valid: Vec[Bool]
a valid flag indicated whether a buff is in-used
- val mshr_state_dnxt: UInt
- val mshr_state_qout: UInt
- def mulNum: Int
- Definition Classes
- HasRiftParameters
- final lazy val name: String
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- BaseModule
- final def ne(arg0: AnyRef): Boolean
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- final def notify(): Unit
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- final def notifyAll(): Unit
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- def opChn: Int
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- implicit val p: Parameters
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- RiftModule → HasRiftParameters
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def plen: Int
- Definition Classes
- HasRiftParameters
- def pmpNum: Int
- Definition Classes
- HasRiftParameters
- def portsContains(elem: Data): Boolean
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- protected
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- BaseModule
- def portsSize: Int
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- protected
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- BaseModule
- final val reset: Reset
- Definition Classes
- Module
- def resetType: Type
- Definition Classes
- Module
- val riftSetting: RiftSetting
- Definition Classes
- HasRiftParameters
- def rnChn: Int
- Definition Classes
- HasRiftParameters
- val rsp_valid: Bool
a register of io.rsp.valid
- def sbEntry: Int
- Definition Classes
- HasDcacheParameters
- def stEntry: Int
- Definition Classes
- HasDcacheParameters
- def suggestName(seed: => String): GetUnit.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- def tag_w: Int
- Definition Classes
- HasDcacheParameters
- def tlbEntry: Int
- Definition Classes
- HasRiftParameters
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- val transCnt: UInt
- val vParams: VectorParameters
- Definition Classes
- HasRiftParameters
- def vRegNum: Int
- Definition Classes
- HasRiftParameters
- def vlen: Int
- Definition Classes
- HasRiftParameters
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
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- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
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- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
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- @throws(classOf[java.lang.InterruptedException])
- def wbChn: Int
- Definition Classes
- HasRiftParameters
- def xRegNum: Int
- Definition Classes
- HasRiftParameters
Deprecated Value Members
- def finalize(): Unit
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- protected[lang]
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- def override_clock: Option[Clock]
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
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- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation