class PutUnit extends RiftModule with HasDcacheParameters
a writeBack Unit accept data and paddr from l1cache and write it back to l2cache Put-Mode
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- new PutUnit(edge: TLEdgeOut, id: Int)(implicit p: Parameters)
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- final def !=(arg0: Any): Boolean
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- final def ##: Int
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- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
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- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
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- def _moduleDefinitionIdentifierProposal: String
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- def _traitModuleDefinitionIdentifierProposal: Option[String]
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- val access_ready: Bool
a register of io.access.ready
- def addr_lsb: Int
- Definition Classes
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- def aluNum: Int
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- final def asInstanceOf[T0]: T0
- Definition Classes
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- val beatCnt: UInt
a n step counter to select data
- def bk: Int
- Definition Classes
- HasDcacheParameters
- def bk_w: Int
- Definition Classes
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- def cb: Int
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- def cb_w: Int
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- def circuitName: String
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- def cl: Int
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- final val clock: Clock
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- def clone(): AnyRef
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- def cmChn: Int
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- val dcacheParams: DcacheParameters
- Definition Classes
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- final val definitionIdentifier: String
- Definition Classes
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- def desiredName: String
- Definition Classes
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- def dptEntry: Int
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- def dw: Int
- Definition Classes
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- def fRegNum: Int
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- def getCommands: Seq[Command]
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- def getModulePorts: Seq[Data]
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- val getPut_valid: Bool
a register of io.getPut.valid
- def hasDebugger: Boolean
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- def hasL2: Boolean
- Definition Classes
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- def hasLRU: Boolean
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- def hasPreFetch: Boolean
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- def hasSeed: Boolean
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- def hashCode(): Int
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- def hasuBTB: Boolean
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- def hpmNum: Int
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- val icacheParams: IcacheParameters
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- val ifParams: IFParameters
- Definition Classes
- HasRiftParameters
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- val io: PutUnitIO
- Definition Classes
- PutUnit → RiftModule
- final def isInstanceOf[T0]: Boolean
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- def isLowPower: Boolean
- Definition Classes
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- def isMinArea: Boolean
- Definition Classes
- HasRiftParameters
- val is_release_done: Bool
a last flag of release transmision
- def l1BeatBits: Int
- Definition Classes
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- def l1DW: Int
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- def line_w: Int
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- def maxRegNum: Int
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- def memBeatBits: Int
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- final lazy val name: String
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- final def notify(): Unit
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- def opChn: Int
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- implicit val p: Parameters
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- RiftModule → HasRiftParameters
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def plen: Int
- Definition Classes
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- def pmpNum: Int
- Definition Classes
- HasRiftParameters
- def portsContains(elem: Data): Boolean
- Attributes
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- def portsSize: Int
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- final val reset: Reset
- Definition Classes
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- def resetType: Type
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- val riftSetting: RiftSetting
- Definition Classes
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- def rnChn: Int
- Definition Classes
- HasRiftParameters
- def sbEntry: Int
- Definition Classes
- HasDcacheParameters
- def stEntry: Int
- Definition Classes
- HasDcacheParameters
- def suggestName(seed: => String): PutUnit.this.type
- Definition Classes
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- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
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- def tag_w: Int
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- def tlbEntry: Int
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- def toString(): String
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- final def toTarget: ModuleTarget
- Definition Classes
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- val vParams: VectorParameters
- Definition Classes
- HasRiftParameters
- def vRegNum: Int
- Definition Classes
- HasRiftParameters
- def vlen: Int
- Definition Classes
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- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
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- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
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- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- def wbChn: Int
- Definition Classes
- HasRiftParameters
- val wb_fifo: Queue[Info_writeBack_req]
a tiny fifo that temporarily store the writeback info from l1cache
- val wb_state_dnxt: UInt
- val wb_state_qout: UInt
- def xRegNum: Int
- Definition Classes
- HasRiftParameters
Deprecated Value Members
- def finalize(): Unit
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- protected[lang]
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- def override_clock: Option[Clock]
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
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- Module
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- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
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- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation