abstract class CommitState extends BaseCommit with UpdateCsrFilesFun with CommitBranch with CommitDebug
commit
- Note
for every commit-chn, it can be: comfirm: commit at this tick abort: cancel and flush at this tick cancel: the perivious chn abort idle: empty line or waitting to check whether is comfirm or abort
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- new CommitState()(implicit p: Parameters)
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- class CommitIO extends Bundle
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- def cmChn: Int
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- val cmm_state: Vec[CMMState_Bundle]
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- val commit_state: Vec[UInt]
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- val commit_state_is_idle: IndexedSeq[Bool]
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- val commit_state_is_misPredict: IndexedSeq[Bool]
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- BaseCommit
- val csr_state: Vec[CSR_Bundle]
- Definition Classes
- BaseCommit
- val csrfiles: CSR_Bundle
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- def update_DMode(in: CMMState_Bundle): Bool
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- UpdateCsrFilesFun
- def update_csrfiles(in: CMMState_Bundle): CSR_Bundle
- Definition Classes
- UpdateCsrFilesFun
- def update_dcsr(in: CMMState_Bundle): DcsrBundle
- Definition Classes
- UpdateCsrFilesFun
- def update_dpc(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_dscratch0(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_dscratch1(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_dscratch2(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_fcsr(in: CMMState_Bundle): FCSRBundle
- Definition Classes
- UpdateCsrFilesFun
- def update_marchid(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_mcause(in: CMMState_Bundle): CauseBundle
Machine Cause Register
Machine Cause Register
when a ***trap*** is taken into ***M-mode***, Indicating the event that caused the trap
- Definition Classes
- UpdateCsrFilesFun
- def update_mcounteren(in: CMMState_Bundle): CounterenBundle
Machine Counter-Enable Register -- mcounteren
Machine Counter-Enable Register -- mcounteren
- Definition Classes
- UpdateCsrFilesFun
- def update_mcountinhibit(in: CMMState_Bundle): UInt
when set, the counter will not increase, all hard-wire to 0 in this version
when set, the counter will not increase, all hard-wire to 0 in this version
- Definition Classes
- UpdateCsrFilesFun
- def update_mcycle(in: CMMState_Bundle): UInt
Hardware Performance Monitor -- mcycle
Hardware Performance Monitor -- mcycle
- returns
the number of clock cycles executed by the processor core
- Definition Classes
- UpdateCsrFilesFun
- def update_medeleg(in: CMMState_Bundle): UInt
Machine Trap Delegation Register
Machine Trap Delegation Register
By default, the exception will be handled in M-mode, when the bits set, it's handled in S-mode
- Definition Classes
- UpdateCsrFilesFun
- def update_mepc(in: CMMState_Bundle): UInt
Machine Exception Program Counter
Machine Exception Program Counter
- Definition Classes
- UpdateCsrFilesFun
- Note
hold all valid virtual addresses when a ***trap*** is taken into ***M-mode***, update to the ***virtual address*** that was interrupted or encountered the exception
,we are only considering 2 condition: 1) 1 trap outsize the DMode; 2) trap inside the DMode; we will not consider normal trap + step, for step-interrupt has one cycle latency
- def update_mhartid(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_mhpmcounter(in: CMMState_Bundle): Vec[UInt]
Hardware Performance Monitor -- mhpmcounter 3~31
Hardware Performance Monitor -- mhpmcounter 3~31
- Definition Classes
- UpdateCsrFilesFun
- def update_mhpmevent(in: CMMState_Bundle): Vec[UInt]
- Definition Classes
- UpdateCsrFilesFun
- def update_mideleg(in: CMMState_Bundle): UInt
Machine Trap Delegation Register
Machine Trap Delegation Register
By default, the interrupt will be handled in M-mode, when the bits set, it's handled in S-mode
- Definition Classes
- UpdateCsrFilesFun
- def update_mie(in: CMMState_Bundle): MSIntBundle
Machine Interrupt Registers
Machine Interrupt Registers
- Definition Classes
- UpdateCsrFilesFun
- def update_mimpid(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_minstret(in: CMMState_Bundle): UInt
Hardware Performance Monitor -- minstret
Hardware Performance Monitor -- minstret
- returns
the number of instructions the hart has retired
- Definition Classes
- UpdateCsrFilesFun
- def update_mip(in: CMMState_Bundle): MSIntBundle
Machine Interrupt Registers
Machine Interrupt Registers
- Definition Classes
- UpdateCsrFilesFun
- Note
implemented in read-only mode
- def update_misa(in: CMMState_Bundle): UInt
Machine ISA register
Machine ISA register
- Definition Classes
- UpdateCsrFilesFun
- Note
U(20): User mode implement S(18): Supervisor mode implemented N(13): User-level interrupts supported
,M(12): Integer Multiply/Divide extension I(8): RV64I base ISA C(2): Compressed extension
- def update_mscratch(in: CMMState_Bundle): UInt
Machine Scratch Register -- mscratch
Machine Scratch Register -- mscratch
it's used to hold a pointer to a M-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler
- Definition Classes
- UpdateCsrFilesFun
- def update_mstatus(in: CMMState_Bundle): MStatusBundle
- Definition Classes
- UpdateCsrFilesFun
- def update_mtinst(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_mtval(in: CMMState_Bundle): UInt
Machine Trap Value Register
Machine Trap Value Register
When a trap is taken into ***M-mode***, update to ***virtual address*** or ***faulting instruction***
- Definition Classes
- UpdateCsrFilesFun
- def update_mtval2(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_mtvec(in: CMMState_Bundle): TVecBundle
Machine Trap-Vector Base-Address Register holds trap vector configuration, consisting of a vector of a vector base address and a bector mode
Machine Trap-Vector Base-Address Register holds trap vector configuration, consisting of a vector of a vector base address and a bector mode
- Definition Classes
- UpdateCsrFilesFun
- def update_mvendorid(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_pmpaddr(in: CMMState_Bundle): Vec[UInt]
- Definition Classes
- UpdateCsrFilesFun
- def update_pmpcfg(in: CMMState_Bundle): Vec[Vec[PmpcfgBundle]]
- Definition Classes
- UpdateCsrFilesFun
- def update_priv_lvl(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_satp(in: CMMState_Bundle): SatpBundle
Supervisor Address protection and translation Register -- satp
Supervisor Address protection and translation Register -- satp
- Definition Classes
- UpdateCsrFilesFun
- def update_scause(in: CMMState_Bundle): CauseBundle
Supervisor Cause Register -- scause
Supervisor Cause Register -- scause
when a trap is taken into S-mode, scause is written with a code indicating the event that cause the trap
- Definition Classes
- UpdateCsrFilesFun
- def update_scounteren(in: CMMState_Bundle): CounterenBundle
Supervisor Timers and Performance Counters -- Counter-Enable Register -- scounteren
Supervisor Timers and Performance Counters -- Counter-Enable Register -- scounteren
- Definition Classes
- UpdateCsrFilesFun
- Note
controls the availability of the hardware performance monitoring counters to U-mode
- def update_sepc(in: CMMState_Bundle): UInt
Supervisor Exception Program Counter -- sepc
Supervisor Exception Program Counter -- sepc
hold virtual addresses: when a trap is taken into S-mode, sepc is written with the virtual address of the instruction that was interrupted or that encountered the exception
- Definition Classes
- UpdateCsrFilesFun
- def update_sscratch(in: CMMState_Bundle): UInt
Supervisor Scratch Register -- sscratch
Supervisor Scratch Register -- sscratch
- Definition Classes
- UpdateCsrFilesFun
- Note
used to hold a pointer to the hart-local supervisor context while the hart is executing user code
- def update_stval(in: CMMState_Bundle): UInt
Supervisor Trap Value Register -- stval
Supervisor Trap Value Register -- stval
when a trap is taken into S-mode, stval is written with exception-specific information to assist softwave in handling the trap
- Definition Classes
- UpdateCsrFilesFun
- def update_stvec(in: CMMState_Bundle): TVecBundle
Supervisor Trap Vector Base Address Register --stvec
Supervisor Trap Vector Base Address Register --stvec
- Definition Classes
- UpdateCsrFilesFun
- Note
holdstrap vector configuration
- def update_tdata1(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_tdata2(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_tdata3(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_tselect(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_vConfig(in: CMMState_Bundle): VConfigBundle
- Definition Classes
- UpdateCsrFilesFun
- def update_vcsr(in: CMMState_Bundle): VCSRBundle
- Definition Classes
- UpdateCsrFilesFun
- def update_vlenb(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_vstart(in: CMMState_Bundle): UInt
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- UpdateCsrFilesFun
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