class Commit extends CommitState with CommitComb with CommitCsrFiles with CommitRegFiles with CommitIFRedirect with CommitInfoMMU with CommitInfoLsu with CommitInfoVec with CommitDiff
- Note
new feature 1. abort can only emmit at chn0 -> abort can emmit at any chn 2. branch/jalr can resolve at any chn but only one of every 3. branch misPredict will redirect at cmm
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- Commit
- CommitDiff
- CommitInfoVec
- CommitInfoLsu
- CommitInfoMMU
- CommitIFRedirect
- CommitRegFiles
- CommitCsrFiles
- CommitComb
- CommitState
- CommitDebug
- CommitBranch
- UpdateCsrFilesFun
- BaseCommit
- RiftModule
- HasRiftParameters
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Instance Constructors
- new Commit()(implicit p: Parameters)
Type Members
- class CommitIO extends Bundle
- Definition Classes
- BaseCommit
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
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- final def ##: Int
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- final def ==(arg0: Any): Boolean
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- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
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- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
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- var _closed: Boolean
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- def _moduleDefinitionIdentifierProposal: String
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- BaseModule
- def _traitModuleDefinitionIdentifierProposal: Option[String]
- Attributes
- protected
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- BaseModule
- val abort_chn: UInt
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- CommitState
- def aluNum: Int
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- def circuitName: String
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- final val clock: Clock
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- def clone(): AnyRef
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- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- def cmChn: Int
- Definition Classes
- HasRiftParameters
- val cmm_state: Vec[CMMState_Bundle]
- Definition Classes
- BaseCommit
- val commit_state: Vec[UInt]
- Definition Classes
- BaseCommit
- val commit_state_is_abort: IndexedSeq[Bool]
- Definition Classes
- BaseCommit
- val commit_state_is_comfirm: IndexedSeq[Bool]
- Definition Classes
- BaseCommit
- val commit_state_is_idle: IndexedSeq[Bool]
- Definition Classes
- BaseCommit
- val commit_state_is_misPredict: IndexedSeq[Bool]
- Definition Classes
- BaseCommit
- val csr_state: Vec[CSR_Bundle]
- Definition Classes
- BaseCommit
- val csrfiles: CSR_Bundle
- Definition Classes
- BaseCommit
- val dcacheParams: DcacheParameters
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- final val definitionIdentifier: String
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- BaseModule
- def desiredName: String
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- BaseModule
- def dptEntry: Int
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- val emu_reset: Bool
- Definition Classes
- CommitDebug
- final def eq(arg0: AnyRef): Boolean
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- def equals(that: Any): Boolean
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- def fRegNum: Int
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- def ftChn: Int
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- def getCommands: Seq[Command]
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- val ifParams: IFParameters
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- def instanceName: String
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- val io: CommitIO
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- val is_retired: IndexedSeq[Bool]
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- BaseCommit
- val is_single_step: Bool
- Definition Classes
- CommitDebug
- val is_trigger: Bool
- Definition Classes
- CommitDebug
- def l1BeatBits: Int
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- def opChn: Int
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- def pathName: String
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- def plen: Int
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- def portsContains(elem: Data): Boolean
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- def portsSize: Int
- Attributes
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- final val reset: Reset
- Definition Classes
- Module
- def resetToDefault(csrfiles: CSR_Bundle): Unit
- Definition Classes
- CommitCsrFiles
- def resetType: Type
- Definition Classes
- Module
- val riftSetting: RiftSetting
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- def rnChn: Int
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- val rtc: Seq[Bool]
- Definition Classes
- CommitCsrFiles
- def suggestName(seed: => String): Commit.this.type
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- def toString(): String
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- final def toTarget: ModuleTarget
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- BaseModule → InstanceId
- def update_DMode(in: CMMState_Bundle): Bool
- Definition Classes
- UpdateCsrFilesFun
- def update_csrfiles(in: CMMState_Bundle): CSR_Bundle
- Definition Classes
- UpdateCsrFilesFun
- def update_dcsr(in: CMMState_Bundle): DcsrBundle
- Definition Classes
- UpdateCsrFilesFun
- def update_dpc(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_dscratch0(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_dscratch1(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_dscratch2(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_fcsr(in: CMMState_Bundle): FCSRBundle
- Definition Classes
- UpdateCsrFilesFun
- def update_marchid(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_mcause(in: CMMState_Bundle): CauseBundle
Machine Cause Register
Machine Cause Register
when a ***trap*** is taken into ***M-mode***, Indicating the event that caused the trap
- Definition Classes
- UpdateCsrFilesFun
- def update_mcounteren(in: CMMState_Bundle): CounterenBundle
Machine Counter-Enable Register -- mcounteren
Machine Counter-Enable Register -- mcounteren
- Definition Classes
- UpdateCsrFilesFun
- def update_mcountinhibit(in: CMMState_Bundle): UInt
when set, the counter will not increase, all hard-wire to 0 in this version
when set, the counter will not increase, all hard-wire to 0 in this version
- Definition Classes
- UpdateCsrFilesFun
- def update_mcycle(in: CMMState_Bundle): UInt
Hardware Performance Monitor -- mcycle
Hardware Performance Monitor -- mcycle
- returns
the number of clock cycles executed by the processor core
- Definition Classes
- UpdateCsrFilesFun
- def update_medeleg(in: CMMState_Bundle): UInt
Machine Trap Delegation Register
Machine Trap Delegation Register
By default, the exception will be handled in M-mode, when the bits set, it's handled in S-mode
- Definition Classes
- UpdateCsrFilesFun
- def update_mepc(in: CMMState_Bundle): UInt
Machine Exception Program Counter
Machine Exception Program Counter
- Definition Classes
- UpdateCsrFilesFun
- Note
hold all valid virtual addresses when a ***trap*** is taken into ***M-mode***, update to the ***virtual address*** that was interrupted or encountered the exception
,we are only considering 2 condition: 1) 1 trap outsize the DMode; 2) trap inside the DMode; we will not consider normal trap + step, for step-interrupt has one cycle latency
- def update_mhartid(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_mhpmcounter(in: CMMState_Bundle): Vec[UInt]
Hardware Performance Monitor -- mhpmcounter 3~31
Hardware Performance Monitor -- mhpmcounter 3~31
- Definition Classes
- UpdateCsrFilesFun
- def update_mhpmevent(in: CMMState_Bundle): Vec[UInt]
- Definition Classes
- UpdateCsrFilesFun
- def update_mideleg(in: CMMState_Bundle): UInt
Machine Trap Delegation Register
Machine Trap Delegation Register
By default, the interrupt will be handled in M-mode, when the bits set, it's handled in S-mode
- Definition Classes
- UpdateCsrFilesFun
- def update_mie(in: CMMState_Bundle): MSIntBundle
Machine Interrupt Registers
Machine Interrupt Registers
- Definition Classes
- UpdateCsrFilesFun
- def update_mimpid(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_minstret(in: CMMState_Bundle): UInt
Hardware Performance Monitor -- minstret
Hardware Performance Monitor -- minstret
- returns
the number of instructions the hart has retired
- Definition Classes
- UpdateCsrFilesFun
- def update_mip(in: CMMState_Bundle): MSIntBundle
Machine Interrupt Registers
Machine Interrupt Registers
- Definition Classes
- UpdateCsrFilesFun
- Note
implemented in read-only mode
- def update_misa(in: CMMState_Bundle): UInt
Machine ISA register
Machine ISA register
- Definition Classes
- UpdateCsrFilesFun
- Note
U(20): User mode implement S(18): Supervisor mode implemented N(13): User-level interrupts supported
,M(12): Integer Multiply/Divide extension I(8): RV64I base ISA C(2): Compressed extension
- def update_mscratch(in: CMMState_Bundle): UInt
Machine Scratch Register -- mscratch
Machine Scratch Register -- mscratch
it's used to hold a pointer to a M-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler
- Definition Classes
- UpdateCsrFilesFun
- def update_mstatus(in: CMMState_Bundle): MStatusBundle
- Definition Classes
- UpdateCsrFilesFun
- def update_mtinst(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_mtval(in: CMMState_Bundle): UInt
Machine Trap Value Register
Machine Trap Value Register
When a trap is taken into ***M-mode***, update to ***virtual address*** or ***faulting instruction***
- Definition Classes
- UpdateCsrFilesFun
- def update_mtval2(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_mtvec(in: CMMState_Bundle): TVecBundle
Machine Trap-Vector Base-Address Register holds trap vector configuration, consisting of a vector of a vector base address and a bector mode
Machine Trap-Vector Base-Address Register holds trap vector configuration, consisting of a vector of a vector base address and a bector mode
- Definition Classes
- UpdateCsrFilesFun
- def update_mvendorid(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_pmpaddr(in: CMMState_Bundle): Vec[UInt]
- Definition Classes
- UpdateCsrFilesFun
- def update_pmpcfg(in: CMMState_Bundle): Vec[Vec[PmpcfgBundle]]
- Definition Classes
- UpdateCsrFilesFun
- def update_priv_lvl(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_satp(in: CMMState_Bundle): SatpBundle
Supervisor Address protection and translation Register -- satp
Supervisor Address protection and translation Register -- satp
- Definition Classes
- UpdateCsrFilesFun
- def update_scause(in: CMMState_Bundle): CauseBundle
Supervisor Cause Register -- scause
Supervisor Cause Register -- scause
when a trap is taken into S-mode, scause is written with a code indicating the event that cause the trap
- Definition Classes
- UpdateCsrFilesFun
- def update_scounteren(in: CMMState_Bundle): CounterenBundle
Supervisor Timers and Performance Counters -- Counter-Enable Register -- scounteren
Supervisor Timers and Performance Counters -- Counter-Enable Register -- scounteren
- Definition Classes
- UpdateCsrFilesFun
- Note
controls the availability of the hardware performance monitoring counters to U-mode
- def update_sepc(in: CMMState_Bundle): UInt
Supervisor Exception Program Counter -- sepc
Supervisor Exception Program Counter -- sepc
hold virtual addresses: when a trap is taken into S-mode, sepc is written with the virtual address of the instruction that was interrupted or that encountered the exception
- Definition Classes
- UpdateCsrFilesFun
- def update_sscratch(in: CMMState_Bundle): UInt
Supervisor Scratch Register -- sscratch
Supervisor Scratch Register -- sscratch
- Definition Classes
- UpdateCsrFilesFun
- Note
used to hold a pointer to the hart-local supervisor context while the hart is executing user code
- def update_stval(in: CMMState_Bundle): UInt
Supervisor Trap Value Register -- stval
Supervisor Trap Value Register -- stval
when a trap is taken into S-mode, stval is written with exception-specific information to assist softwave in handling the trap
- Definition Classes
- UpdateCsrFilesFun
- def update_stvec(in: CMMState_Bundle): TVecBundle
Supervisor Trap Vector Base Address Register --stvec
Supervisor Trap Vector Base Address Register --stvec
- Definition Classes
- UpdateCsrFilesFun
- Note
holdstrap vector configuration
- def update_tdata1(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_tdata2(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_tdata3(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_tselect(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_vConfig(in: CMMState_Bundle): VConfigBundle
- Definition Classes
- UpdateCsrFilesFun
- def update_vcsr(in: CMMState_Bundle): VCSRBundle
- Definition Classes
- UpdateCsrFilesFun
- def update_vlenb(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- def update_vstart(in: CMMState_Bundle): UInt
- Definition Classes
- UpdateCsrFilesFun
- val vParams: VectorParameters
- Definition Classes
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- def vRegNum: Int
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- def vlen: Int
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- final def wait(arg0: Long, arg1: Int): Unit
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- final def wait(arg0: Long): Unit
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- final def wait(): Unit
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- def wbChn: Int
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- def override_clock: Option[Clock]
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(Since version Chisel 3.5) Use withClock at Module instantiation
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(Since version Chisel 3.5) Use withClock at Module instantiation
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(Since version Chisel 3.5) Use withClock at Module instantiation
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(Since version Chisel 3.5) Use withClock at Module instantiation