t

rift2Core.privilege

UpdateCsrFilesFun

trait UpdateCsrFilesFun extends AnyRef

Self Type
UpdateCsrFilesFun with BaseCommit
Linear Supertypes
AnyRef, Any
Known Subclasses
Commit, CommitState
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. UpdateCsrFilesFun
  2. AnyRef
  3. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. Protected

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  5. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
  6. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  7. def equals(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef → Any
  8. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  9. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  10. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  11. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  12. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  13. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  14. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  15. def toString(): String
    Definition Classes
    AnyRef → Any
  16. def update_DMode(in: CMMState_Bundle): Bool
  17. def update_csrfiles(in: CMMState_Bundle): CSR_Bundle
  18. def update_dcsr(in: CMMState_Bundle): DcsrBundle
  19. def update_dpc(in: CMMState_Bundle): UInt
  20. def update_dscratch0(in: CMMState_Bundle): UInt
  21. def update_dscratch1(in: CMMState_Bundle): UInt
  22. def update_dscratch2(in: CMMState_Bundle): UInt
  23. def update_fcsr(in: CMMState_Bundle): FCSRBundle
  24. def update_marchid(in: CMMState_Bundle): UInt
  25. def update_mcause(in: CMMState_Bundle): CauseBundle

    Machine Cause Register

    Machine Cause Register

    when a ***trap*** is taken into ***M-mode***, Indicating the event that caused the trap

  26. def update_mcounteren(in: CMMState_Bundle): CounterenBundle

    Machine Counter-Enable Register -- mcounteren

  27. def update_mcountinhibit(in: CMMState_Bundle): UInt

    when set, the counter will not increase, all hard-wire to 0 in this version

  28. def update_mcycle(in: CMMState_Bundle): UInt

    Hardware Performance Monitor -- mcycle

    Hardware Performance Monitor -- mcycle

    returns

    the number of clock cycles executed by the processor core

  29. def update_medeleg(in: CMMState_Bundle): UInt

    Machine Trap Delegation Register

    Machine Trap Delegation Register

    By default, the exception will be handled in M-mode, when the bits set, it's handled in S-mode

  30. def update_mepc(in: CMMState_Bundle): UInt

    Machine Exception Program Counter

    Machine Exception Program Counter

    Note

    hold all valid virtual addresses when a ***trap*** is taken into ***M-mode***, update to the ***virtual address*** that was interrupted or encountered the exception

    ,

    we are only considering 2 condition: 1) 1 trap outsize the DMode; 2) trap inside the DMode; we will not consider normal trap + step, for step-interrupt has one cycle latency

  31. def update_mhartid(in: CMMState_Bundle): UInt
  32. def update_mhpmcounter(in: CMMState_Bundle): Vec[UInt]

    Hardware Performance Monitor -- mhpmcounter 3~31

  33. def update_mhpmevent(in: CMMState_Bundle): Vec[UInt]
  34. def update_mideleg(in: CMMState_Bundle): UInt

    Machine Trap Delegation Register

    Machine Trap Delegation Register

    By default, the interrupt will be handled in M-mode, when the bits set, it's handled in S-mode

  35. def update_mie(in: CMMState_Bundle): MSIntBundle

    Machine Interrupt Registers

  36. def update_mimpid(in: CMMState_Bundle): UInt
  37. def update_minstret(in: CMMState_Bundle): UInt

    Hardware Performance Monitor -- minstret

    Hardware Performance Monitor -- minstret

    returns

    the number of instructions the hart has retired

  38. def update_mip(in: CMMState_Bundle): MSIntBundle

    Machine Interrupt Registers

    Machine Interrupt Registers

    Note

    implemented in read-only mode

  39. def update_misa(in: CMMState_Bundle): UInt

    Machine ISA register

    Machine ISA register

    Note

    U(20): User mode implement S(18): Supervisor mode implemented N(13): User-level interrupts supported

    ,

    M(12): Integer Multiply/Divide extension I(8): RV64I base ISA C(2): Compressed extension

  40. def update_mscratch(in: CMMState_Bundle): UInt

    Machine Scratch Register -- mscratch

    Machine Scratch Register -- mscratch

    it's used to hold a pointer to a M-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler

  41. def update_mstatus(in: CMMState_Bundle): MStatusBundle
  42. def update_mtinst(in: CMMState_Bundle): UInt
  43. def update_mtval(in: CMMState_Bundle): UInt

    Machine Trap Value Register

    Machine Trap Value Register

    When a trap is taken into ***M-mode***, update to ***virtual address*** or ***faulting instruction***

  44. def update_mtval2(in: CMMState_Bundle): UInt
  45. def update_mtvec(in: CMMState_Bundle): TVecBundle

    Machine Trap-Vector Base-Address Register holds trap vector configuration, consisting of a vector of a vector base address and a bector mode

  46. def update_mvendorid(in: CMMState_Bundle): UInt
  47. def update_pmpaddr(in: CMMState_Bundle): Vec[UInt]
  48. def update_pmpcfg(in: CMMState_Bundle): Vec[Vec[PmpcfgBundle]]
  49. def update_priv_lvl(in: CMMState_Bundle): UInt
  50. def update_satp(in: CMMState_Bundle): SatpBundle

    Supervisor Address protection and translation Register -- satp

  51. def update_scause(in: CMMState_Bundle): CauseBundle

    Supervisor Cause Register -- scause

    Supervisor Cause Register -- scause

    when a trap is taken into S-mode, scause is written with a code indicating the event that cause the trap

  52. def update_scounteren(in: CMMState_Bundle): CounterenBundle

    Supervisor Timers and Performance Counters -- Counter-Enable Register -- scounteren

    Supervisor Timers and Performance Counters -- Counter-Enable Register -- scounteren

    Note

    controls the availability of the hardware performance monitoring counters to U-mode

  53. def update_sepc(in: CMMState_Bundle): UInt

    Supervisor Exception Program Counter -- sepc

    Supervisor Exception Program Counter -- sepc

    hold virtual addresses: when a trap is taken into S-mode, sepc is written with the virtual address of the instruction that was interrupted or that encountered the exception

  54. def update_sscratch(in: CMMState_Bundle): UInt

    Supervisor Scratch Register -- sscratch

    Supervisor Scratch Register -- sscratch

    Note

    used to hold a pointer to the hart-local supervisor context while the hart is executing user code

  55. def update_stval(in: CMMState_Bundle): UInt

    Supervisor Trap Value Register -- stval

    Supervisor Trap Value Register -- stval

    when a trap is taken into S-mode, stval is written with exception-specific information to assist softwave in handling the trap

  56. def update_stvec(in: CMMState_Bundle): TVecBundle

    Supervisor Trap Vector Base Address Register --stvec

    Supervisor Trap Vector Base Address Register --stvec

    Note

    holdstrap vector configuration

  57. def update_tdata1(in: CMMState_Bundle): UInt
  58. def update_tdata2(in: CMMState_Bundle): UInt
  59. def update_tdata3(in: CMMState_Bundle): UInt
  60. def update_tselect(in: CMMState_Bundle): UInt
  61. def update_vConfig(in: CMMState_Bundle): VConfigBundle
  62. def update_vcsr(in: CMMState_Bundle): VCSRBundle
  63. def update_vlenb(in: CMMState_Bundle): UInt
  64. def update_vstart(in: CMMState_Bundle): UInt
  65. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  66. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException]) @native()
  67. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable]) @Deprecated
    Deprecated

Inherited from AnyRef

Inherited from Any

Ungrouped