class Rift2CoreImp extends Rift2CoreImpBase with Rift2CoreImpFrontend with Rift2CoreImpBackend with Rift2CoreImpPredict with Rift2CoreImpBus with Rift2CoreImpMMU with Rift2CoreImpCommit
Linear Supertypes
Ordering
- Alphabetic
- By Inheritance
Inherited
- Rift2CoreImp
- Rift2CoreImpCommit
- Rift2CoreImpMMU
- Rift2CoreImpBus
- Rift2CoreImpPredict
- Rift2CoreImpBackend
- Rift2CoreImpFrontend
- Rift2CoreImpBase
- HasRiftParameters
- LazyModuleImp
- LazyModuleImpLike
- Module
- RawModule
- BaseModule
- IsInstantiable
- HasId
- InstanceId
- AnyRef
- Any
- Hide All
- Show All
Visibility
- Public
- Protected
Instance Constructors
Type Members
- class Rift2CoreIO extends Bundle
- Definition Classes
- Rift2CoreImpBase
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
- Attributes
- protected
- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _moduleDefinitionIdentifierProposal: String
- Attributes
- protected
- Definition Classes
- BaseModule
- def _traitModuleDefinitionIdentifierProposal: Option[String]
- Attributes
- protected
- Definition Classes
- BaseModule
- def aluNum: Int
- Definition Classes
- HasRiftParameters
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- val auto: AutoBundle
- Definition Classes
- LazyModuleImp → LazyModuleImpLike
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- final val clock: Clock
- Definition Classes
- Module
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- def cmChn: Int
- Definition Classes
- HasRiftParameters
- val cmm_stage: Commit
- Definition Classes
- Rift2CoreImpBase
- val dangles: List[Dangle]
- Definition Classes
- LazyModuleImp → LazyModuleImpLike
- val dcacheParams: DcacheParameters
- Definition Classes
- HasRiftParameters
- val dcache_bus: TLBundle
- Definition Classes
- Rift2CoreImpBase
- val dcache_edge: TLEdgeOut
- Definition Classes
- Rift2CoreImpBase
- final val definitionIdentifier: String
- Definition Classes
- BaseModule
- def desiredName: String
- Definition Classes
- LazyModuleImpLike → BaseModule
- val diff: diff
- Definition Classes
- Rift2CoreImpBase
- def dptEntry: Int
- Definition Classes
- HasRiftParameters
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- val exe_stage: Execute
- Definition Classes
- Rift2CoreImpBase
- def fRegNum: Int
- Definition Classes
- HasRiftParameters
- def fpuNum: Int
- Definition Classes
- HasRiftParameters
- def ftChn: Int
- Definition Classes
- HasRiftParameters
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def hasDebugger: Boolean
- Definition Classes
- HasRiftParameters
- def hasL2: Boolean
- Definition Classes
- HasRiftParameters
- def hasLRU: Boolean
- Definition Classes
- HasRiftParameters
- def hasPreFetch: Boolean
- Definition Classes
- HasRiftParameters
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hasVector: Boolean
- Definition Classes
- HasRiftParameters
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def hasuBTB: Boolean
- Definition Classes
- HasRiftParameters
- def hpmNum: Int
- Definition Classes
- HasRiftParameters
- val i_mmu: MMU
- Definition Classes
- Rift2CoreImpBase
- val icacheParams: IcacheParameters
- Definition Classes
- HasRiftParameters
- val icache_bus: TLBundle
- Definition Classes
- Rift2CoreImpBase
- val icache_edge: TLEdgeOut
- Definition Classes
- Rift2CoreImpBase
- val if1: IF1Base
- Definition Classes
- Rift2CoreImpBase
- val if2: IF2
- Definition Classes
- Rift2CoreImpBase
- val if3: IF3
- Definition Classes
- Rift2CoreImpBase
- val if4: IF4
- Definition Classes
- Rift2CoreImpBase
- val ifParams: IFParameters
- Definition Classes
- HasRiftParameters
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- def instantiate(): (AutoBundle, List[Dangle])
- Attributes
- protected[diplomacy]
- Definition Classes
- LazyModuleImpLike
- val io: Rift2CoreIO
- Definition Classes
- Rift2CoreImpBase
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- def isLowPower: Boolean
- Definition Classes
- HasRiftParameters
- def isMinArea: Boolean
- Definition Classes
- HasRiftParameters
- val iss_stage: Issue
- Definition Classes
- Rift2CoreImpBase
- val iwb_stage: WriteBack
- Definition Classes
- Rift2CoreImpBase
- def l1BeatBits: Int
- Definition Classes
- HasRiftParameters
- def l1DW: Int
- Definition Classes
- HasRiftParameters
- def maxRegNum: Int
- Definition Classes
- HasRiftParameters
- def memBeatBits: Int
- Definition Classes
- HasRiftParameters
- val mmu_bus: TLBundle
- Definition Classes
- Rift2CoreImpBase
- val mmu_edge: TLEdgeOut
- Definition Classes
- Rift2CoreImpBase
- def mulNum: Int
- Definition Classes
- HasRiftParameters
- final lazy val name: String
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def opChn: Int
- Definition Classes
- HasRiftParameters
- implicit val p: Parameters
- Definition Classes
- LazyModuleImpLike
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- val periph_bus: TLBundle
- Definition Classes
- Rift2CoreImpBase
- val periph_edge: TLEdgeOut
- Definition Classes
- Rift2CoreImpBase
- def plen: Int
- Definition Classes
- HasRiftParameters
- def pmpNum: Int
- Definition Classes
- HasRiftParameters
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- val preIssue_stage: RiftModule { def io: rift2Core.backend.VecPreIssueIO }
- Definition Classes
- Rift2CoreImpBase
- val preRename_stage: RiftModule { def io: rift2Core.backend.VecPreRenameIO }
- Definition Classes
- Rift2CoreImpBase
- val prefetch_bus: TLBundle
- Definition Classes
- Rift2CoreImpBase
- val prefetch_edge: TLEdgeOut
- Definition Classes
- Rift2CoreImpBase
- val prefetcher: PreFetcher
- Definition Classes
- Rift2CoreImpBus
- final val reset: Reset
- Definition Classes
- Module
- def resetType: Type
- Definition Classes
- Module
- val riftSetting: RiftSetting
- Definition Classes
- HasRiftParameters
- def rnChn: Int
- Definition Classes
- HasRiftParameters
- val rnm_stage: Rename
- Definition Classes
- Rift2CoreImpBase
- def suggestName(seed: => String): Rift2CoreImp.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val system_bus: TLBundle
- Definition Classes
- Rift2CoreImpBase
- val system_edge: TLEdgeOut
- Definition Classes
- Rift2CoreImpBase
- def tlbEntry: Int
- Definition Classes
- HasRiftParameters
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- val vParams: VectorParameters
- Definition Classes
- HasRiftParameters
- def vRegNum: Int
- Definition Classes
- HasRiftParameters
- def vlen: Int
- Definition Classes
- HasRiftParameters
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- def wbChn: Int
- Definition Classes
- HasRiftParameters
- val wrapper: LazyModule
- Definition Classes
- LazyModuleImp → LazyModuleImpLike
- def xRegNum: Int
- Definition Classes
- HasRiftParameters
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation