class IF2 extends IF2Base with IF2MMU with IF2Fault with IF2FSM with IF2ICache with IF2Bus with IF2LoadIBuf with IF2Fence with IF2PreFetch
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Inherited
- IF2
- IF2PreFetch
- IF2Fence
- IF2LoadIBuf
- IF2Bus
- IF2ICache
- IF2FSM
- IF2Fault
- IF2MMU
- IF2Base
- IcacheModule
- HasIcacheParameters
- HasRiftParameters
- Module
- RawModule
- BaseModule
- IsInstantiable
- HasId
- InstanceId
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Visibility
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Instance Constructors
- new IF2(edge: TLEdgeOut)(implicit p: Parameters)
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
- Attributes
- protected
- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _moduleDefinitionIdentifierProposal: String
- Attributes
- protected
- Definition Classes
- BaseModule
- def _traitModuleDefinitionIdentifierProposal: Option[String]
- Attributes
- protected
- Definition Classes
- BaseModule
- def addr_lsb: Int
- Definition Classes
- HasIcacheParameters
- def aluNum: Int
- Definition Classes
- HasRiftParameters
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def bk: Int
- Definition Classes
- HasIcacheParameters
- def cb: Int
- Definition Classes
- HasIcacheParameters
- val cb_em: UInt
- Definition Classes
- IF2ICache
- val cb_sel: UInt
- Definition Classes
- IF2ICache
- def cb_w: Int
- Definition Classes
- HasIcacheParameters
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- def cl: Int
- Definition Classes
- HasIcacheParameters
- val cl_sel: UInt
- Definition Classes
- IF2Base
- final val clock: Clock
- Definition Classes
- Module
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- def cmChn: Int
- Definition Classes
- HasRiftParameters
- val datRAM: IndexedSeq[DatRAM]
- Definition Classes
- IF2ICache
- val dcacheParams: DcacheParameters
- Definition Classes
- HasRiftParameters
- final val definitionIdentifier: String
- Definition Classes
- BaseModule
- def desiredName: String
- Definition Classes
- BaseModule
- def dptEntry: Int
- Definition Classes
- HasRiftParameters
- def dw: Int
- Definition Classes
- HasIcacheParameters
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- def fRegNum: Int
- Definition Classes
- HasRiftParameters
- val fault_lock: Bool
- Definition Classes
- IF2Base
- def fpuNum: Int
- Definition Classes
- HasRiftParameters
- def ftChn: Int
- Definition Classes
- HasRiftParameters
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def hasDebugger: Boolean
- Definition Classes
- HasRiftParameters
- def hasL2: Boolean
- Definition Classes
- HasRiftParameters
- def hasLRU: Boolean
- Definition Classes
- HasRiftParameters
- def hasPreFetch: Boolean
- Definition Classes
- HasRiftParameters
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hasVector: Boolean
- Definition Classes
- HasRiftParameters
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def hasuBTB: Boolean
- Definition Classes
- HasRiftParameters
- val hit_sel: UInt
convert one hot hit to UInt
convert one hot hit to UInt
- Definition Classes
- IF2Base
- def hpmNum: Int
- Definition Classes
- HasRiftParameters
- val iEdge: TLEdgeOut
- Definition Classes
- IF2Base
- val ibuf: MultiPortFifo[IF2_Bundle]
- Definition Classes
- IF2Base
- val icacheParams: IcacheParameters
- Definition Classes
- HasRiftParameters
- val icache_access_data: UInt
- Definition Classes
- IF2Base
- val icache_access_data_lo: Vec[UInt]
- Definition Classes
- IF2Base
- val icache_sramrd_data: UInt
- Definition Classes
- IF2Base
- val icache_state_dnxt: UInt
- Definition Classes
- IF2Base
- val icache_state_qout: UInt
- Definition Classes
- IF2Base
- val ifParams: IFParameters
- Definition Classes
- HasRiftParameters
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- val io: IF2IO
- Definition Classes
- IF2Base → IcacheModule
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- def isLowPower: Boolean
- Definition Classes
- HasRiftParameters
- def isMinArea: Boolean
- Definition Classes
- HasRiftParameters
- val is_access_fault: Bool
- Definition Classes
- IF2Base
- val is_emptyBlock_exist_r: Bool
- Definition Classes
- IF2ICache
- val is_hit: Bool
flag that indicated that if there is a cache block hit
flag that indicated that if there is a cache block hit
- Definition Classes
- IF2Base
- val is_hit_oh: Vec[Bool]
one hot code indicated which blcok is hit
one hot code indicated which blcok is hit
- Definition Classes
- IF2Base
- val is_paging_fault: Bool
- Definition Classes
- IF2Base
- val is_trans_done: Bool
Count the memory transactions using TLEdgeOut object.
Count the memory transactions using TLEdgeOut object.
- Definition Classes
- IF2Base
- val is_valid: Vec[Vec[Bool]]
flag that indicated that if a cache block is valid
flag that indicated that if a cache block is valid
- Definition Classes
- IF2ICache
- val kill_trans: Bool
- Definition Classes
- IF2Base
- def l1BeatBits: Int
- Definition Classes
- HasRiftParameters
- def l1DW: Int
- Definition Classes
- HasRiftParameters
- def line_w: Int
- Definition Classes
- HasIcacheParameters
- def maxRegNum: Int
- Definition Classes
- HasRiftParameters
- def memBeatBits: Int
- Definition Classes
- HasRiftParameters
- def mulNum: Int
- Definition Classes
- HasRiftParameters
- final lazy val name: String
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def opChn: Int
- Definition Classes
- HasRiftParameters
- implicit val p: Parameters
- Definition Classes
- IcacheModule → HasRiftParameters
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def plen: Int
- Definition Classes
- HasRiftParameters
- def pmpNum: Int
- Definition Classes
- HasRiftParameters
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- val reAlign_instr: UInt
- Definition Classes
- IF2LoadIBuf
- final val reset: Reset
- Definition Classes
- Module
- def resetType: Type
- Definition Classes
- Module
- val riftSetting: RiftSetting
- Definition Classes
- HasRiftParameters
- def rnChn: Int
- Definition Classes
- HasRiftParameters
- val rpl_sel: UInt
- Definition Classes
- IF2ICache
- def suggestName(seed: => String): IF2.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val tagRAM: IndexedSeq[TagRAM]
- Definition Classes
- IF2ICache
- val tag_sel: UInt
- Definition Classes
- IF2Base
- def tag_w: Int
- Definition Classes
- HasIcacheParameters
- def tlbEntry: Int
- Definition Classes
- HasRiftParameters
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- val transCnt: UInt
Count the memory transactions using TLEdgeOut object.
Count the memory transactions using TLEdgeOut object.
- Definition Classes
- IF2Base
- val vParams: VectorParameters
- Definition Classes
- HasRiftParameters
- def vRegNum: Int
- Definition Classes
- HasRiftParameters
- def vlen: Int
- Definition Classes
- HasRiftParameters
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- def wbChn: Int
- Definition Classes
- HasRiftParameters
- def xRegNum: Int
- Definition Classes
- HasRiftParameters
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation