class IF4 extends IF4Base with IF4_Decode with IF4_Predict with IF4SRAM
Linear Supertypes
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- IF4
- IF4SRAM
- IF4_Predict
- IF4_Decode
- IF4Base
- IFetchModule
- HasIFParameters
- RiftModule
- HasRiftParameters
- Module
- RawModule
- BaseModule
- IsInstantiable
- HasId
- InstanceId
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- Any
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Visibility
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Instance Constructors
- new IF4()(implicit p: Parameters)
Type Members
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
- Attributes
- protected
- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _moduleDefinitionIdentifierProposal: String
- Attributes
- protected
- Definition Classes
- BaseModule
- def _traitModuleDefinitionIdentifierProposal: Option[String]
- Attributes
- protected
- Definition Classes
- BaseModule
- def aluNum: Int
- Definition Classes
- HasRiftParameters
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- val bRePort: RePort[Branch_FTarget_Bundle]
- Definition Classes
- IF4Base
- val bftq: MultiPortFifo[Branch_FTarget_Bundle]
- Definition Classes
- IF4Base
- val bimRedirect: Vec[DecoupledIO[BIMResp_Bundle]]
- Definition Classes
- IF4Base
- def bim_cl: Int
- Definition Classes
- HasIFParameters
- val bim_decode: IndexedSeq[BIMResp_Bundle]
- Definition Classes
- IF4Base
- val btbRedirect: Vec[DecoupledIO[BTBResp_Bundle]]
- Definition Classes
- IF4Base
- def btb_cl: Int
- Definition Classes
- HasIFParameters
- val btb_decode: IndexedSeq[BTBResp_Bundle]
- Definition Classes
- IF4Base
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- final val clock: Clock
- Definition Classes
- Module
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- def cmChn: Int
- Definition Classes
- HasRiftParameters
- val dcacheParams: DcacheParameters
- Definition Classes
- HasRiftParameters
- final val definitionIdentifier: String
- Definition Classes
- BaseModule
- def desiredName: String
- Definition Classes
- BaseModule
- def dptEntry: Int
- Definition Classes
- HasRiftParameters
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- def fRegNum: Int
- Definition Classes
- HasRiftParameters
- def fpuNum: Int
- Definition Classes
- HasRiftParameters
- def ftChn: Int
- Definition Classes
- HasRiftParameters
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- val ghist: IndexedSeq[UInt]
- Definition Classes
- IF4Base
- def hasDebugger: Boolean
- Definition Classes
- HasRiftParameters
- def hasL2: Boolean
- Definition Classes
- HasRiftParameters
- def hasLRU: Boolean
- Definition Classes
- HasRiftParameters
- def hasPreFetch: Boolean
- Definition Classes
- HasRiftParameters
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hasVector: Boolean
- Definition Classes
- HasRiftParameters
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def hasuBTB: Boolean
- Definition Classes
- HasRiftParameters
- def hpmNum: Int
- Definition Classes
- HasRiftParameters
- val icacheParams: IcacheParameters
- Definition Classes
- HasRiftParameters
- val ifParams: IFParameters
- Definition Classes
- HasRiftParameters
- val imm: IndexedSeq[UInt]
- Definition Classes
- IF4Base
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- val instr_fifo: MultiPortFifo[IF4_Bundle]
- Definition Classes
- IF4Base
- val io: IF4IO
- Definition Classes
- IF4Base → RiftModule
- val isDisAgreeWithIF1: Vec[Bool]
- Definition Classes
- IF4_Predict
- val isIf4Redirect: Vec[Bool]
- Definition Classes
- IF4_Predict
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- def isLowPower: Boolean
- Definition Classes
- HasRiftParameters
- def isMinArea: Boolean
- Definition Classes
- HasRiftParameters
- val isRedirect: Vec[Bool]
- Definition Classes
- IF4_Predict
- val is_bTaken: IndexedSeq[Bool]
- Definition Classes
- IF4_Predict
- val is_branch: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val is_call: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val is_fencei: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val is_jal: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val is_jalr: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val is_req_bim: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val is_req_btb: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val is_req_tage: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val is_return: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val is_rvc: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val is_sfencevma: IndexedSeq[Bool]
- Definition Classes
- IF4Base
- val jRePort: RePort[Jump_FTarget_Bundle]
- Definition Classes
- IF4Base
- val jalr_pc: IndexedSeq[UInt]
- Definition Classes
- IF4_Predict
- val jftq: MultiPortFifo[Jump_FTarget_Bundle]
- Definition Classes
- IF4Base
- def l1BeatBits: Int
- Definition Classes
- HasRiftParameters
- def l1DW: Int
- Definition Classes
- HasRiftParameters
- def maxRegNum: Int
- Definition Classes
- HasRiftParameters
- def memBeatBits: Int
- Definition Classes
- HasRiftParameters
- def mulNum: Int
- Definition Classes
- HasRiftParameters
- final lazy val name: String
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def opChn: Int
- Definition Classes
- HasRiftParameters
- implicit val p: Parameters
- Definition Classes
- RiftModule → HasRiftParameters
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- val pc: IndexedSeq[UInt]
- Definition Classes
- IF4Base
- def plen: Int
- Definition Classes
- HasRiftParameters
- def pmpNum: Int
- Definition Classes
- HasRiftParameters
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- val preDecodeAgn: IndexedSeq[PreDecode_Bundle]
- Definition Classes
- IF4Base
- val ras: RAS
- Definition Classes
- IF4Base
- def ras_dp: Int
- Definition Classes
- HasIFParameters
- val redirectTarget: Vec[UInt]
- Definition Classes
- IF4_Predict
- final val reset: Reset
- Definition Classes
- Module
- def resetType: Type
- Definition Classes
- Module
- val riftSetting: RiftSetting
- Definition Classes
- HasRiftParameters
- def rnChn: Int
- Definition Classes
- HasRiftParameters
- def suggestName(seed: => String): IF4.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val tageRedirect: Vec[DecoupledIO[Vec[TageTableResp_Bundle]]]
- Definition Classes
- IF4Base
- val tage_decode: IndexedSeq[TageResp_Bundle]
- Definition Classes
- IF4Base
- def tage_table: Int
- Definition Classes
- HasIFParameters
- def tlbEntry: Int
- Definition Classes
- HasRiftParameters
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- def uBTB_entry: Int
- Definition Classes
- HasIFParameters
- def uBTB_tag_w: Int
- Definition Classes
- HasIFParameters
- val vParams: VectorParameters
- Definition Classes
- HasRiftParameters
- def vRegNum: Int
- Definition Classes
- HasRiftParameters
- def vlen: Int
- Definition Classes
- HasRiftParameters
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- def wbChn: Int
- Definition Classes
- HasRiftParameters
- def xRegNum: Int
- Definition Classes
- HasRiftParameters
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation