class AXI_slv_r extends Module
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Instance Constructors
- new AXI_slv_r(addrw: Int, dw: Int, idw: Int = 1, usw: Int = 1)
Value Members
- final def !=(arg0: Any): Boolean
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- AnyRef → Any
- final def ##: Int
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- final def ==(arg0: Any): Boolean
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- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
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- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo): Unit
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- var _closed: Boolean
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- def _moduleDefinitionIdentifierProposal: String
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- protected
- Definition Classes
- BaseModule
- def _traitModuleDefinitionIdentifierProposal: Option[String]
- Attributes
- protected
- Definition Classes
- BaseModule
- def addr_lsb: Int
- val ar_ack: Bool
- val araddr: UInt
- val arburst: UInt
- val arlen: UInt
- val arlen_cnt: UInt
- val arready: Bool
- final def asInstanceOf[T0]: T0
- Definition Classes
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- def circuitName: String
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- protected
- Definition Classes
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- final val clock: Clock
- Definition Classes
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- def clone(): AnyRef
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- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- final val definitionIdentifier: String
- Definition Classes
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- def desiredName: String
- Definition Classes
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- final def eq(arg0: AnyRef): Boolean
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- def equals(that: Any): Boolean
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- final def getClass(): Class[_ <: AnyRef]
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- @native() @HotSpotIntrinsicCandidate()
- def getCommands: Seq[Command]
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- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
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- def hasSeed: Boolean
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- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- val io: Bundle { ... /* 5 definitions in type refinement */ }
- final def isInstanceOf[T0]: Boolean
- Definition Classes
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- val is_busy: Bool
- final lazy val name: String
- Definition Classes
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- final def ne(arg0: AnyRef): Boolean
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- final def notify(): Unit
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- final def notifyAll(): Unit
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- def parentModName: String
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- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- val r_ack: Bool
- final val reset: Reset
- Definition Classes
- Module
- def resetType: Type
- Definition Classes
- Module
- val rlast: Bool
- val rvalid: Bool
- def suggestName(seed: => String): AXI_slv_r.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
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- final def toAbsoluteTarget: IsModule
- Definition Classes
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- final def toNamed: ModuleName
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- def toString(): String
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- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
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- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
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- @throws(classOf[java.lang.InterruptedException])
Deprecated Value Members
- def finalize(): Unit
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- protected[lang]
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- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation