class AXI_sim_mem extends AXI_full_mem
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Instance Constructors
- new AXI_sim_mem(dw: Int, aw: Int)
Value Members
- final def !=(arg0: Any): Boolean
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- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo): T
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- def desiredName: String
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- def getCommands: Seq[Command]
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- val io: Bundle { ... /* 5 definitions in type refinement */ }
- Definition Classes
- AXI_full_mem
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val mem_slv_r: AXI_slv_r
- Definition Classes
- AXI_full_mem
- val mem_slv_w: AXI_slv_w
- Definition Classes
- AXI_full_mem
- final lazy val name: String
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
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- def portsContains(elem: Data): Boolean
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- BaseModule
- def portsSize: Int
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- protected
- Definition Classes
- BaseModule
- val ram: DPSram
- Definition Classes
- AXI_sim_mem → AXI_full_mem
- final val reset: Reset
- Definition Classes
- Module
- def resetType: Type
- Definition Classes
- Module
- def suggestName(seed: => String): AXI_sim_mem.this.type
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- final def synchronized[T0](arg0: => T0): T0
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Deprecated Value Members
- def finalize(): Unit
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- def override_clock: Option[Clock]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation